-- Hauptbaustein regchange library IEEE; use IEEE.std_logic_1164.all; USE ieee.std_logic_arith.all; entity regchange is port ( e: in STD_LOGIC_VECTOR (7 downto 0); a: out STD_LOGIC_VECTOR (7 downto 0); cs: in STD_LOGIC ); end regchange; architecture arch_regchange of regchange is signal r : STD_LOGIC_VECTOR (7 downto 0 ) := "XXXXXXXX"; begin process(cs) begin if cs'event and cs = '1' then if (e /= r) then r <= e; a <= e; else r <= r; a <= r; end if; end if; end process; end arch_regchange;